For many electronic systems, it is necessary to control the electromagnetic emissions in order to fulfill electromagnetic interference (EMI) standards. Conventional systems and methods typically use EMI-filter ferrite beads or apply specific shielding techniques on printed circuit boards.
It is further known that electromagnetic interference can be reduced, if clock signals are modulated according to a spread spectrum pattern. The clock spectrum is then spread which reduces the maximum peak power of the clock signal in a specific frequency band around the nominal clock frequency. This well known principle is also referred to as spread-spectrum-clocking (SSC). SSC makes it possible to meet EMI standard requirements with a reduced number and complexity of EMI filter components. This reduces the costs of the electronic systems.
FIG. 1 shows a simplified clock diagram of a prior art configuration for producing spread spectrum modulated clock signals. There is a clock generator TCXO producing a stable clock signal FX which might be divided by a factor R. The divided clock signal FR is then passed to a phase locked loop (PLL). The phase locked loop includes a phase detector, a loop filter, a buffer and a voltage controlled oscillator VCO, as well as a phase interpolator and a further divider. The output signal FVCO of the VCO is phase interpolated, divided by factor N and fed to the phase detector. There is further a spread spectrum modulation stage SSC-MOD which interacts with the divider and the phase interpolator in order to modulate the signal that is fed back to the phase detector. Accordingly, the whole phase locked loop is controlled so as to produce a spread spectrum modulated output signal FVCO. Some systems require multiple spread spectrum clock modulated signals which are to be modulated by individual different schemes. With the approach shown in FIG. 1, this would require numerous phase locked loops and SSC modulation stages in order to provide the required modulated signals. Chip area, power consumption and complexity of the circuits however would increase substantially, if the circuit of FIG. 1 was integrated multiple times on the same integrated circuit.